| VECTOR | [3-0-0:3] |
|---|---|
| PREVIOUS CODE | MICS 6000S |
| DESCRIPTION | This course will focus on the circuits and architectures for high-speed wireline data communications. The topics that will be covered in this course include wireline data link systems, transmitters, receivers, equalizers, clock and data recovery, etc. Upon finishing this course, students are expected to understand the basic principles of modern high-speed data link systems and grasp the essentials to design the integrated circuits for such systems. |
| Section | Date & Time | Room | Instructor | Quota | Enrol | Avail | Wait | Remarks |
|---|---|---|---|---|---|---|---|---|
| L01 (6075) | Mo 01:30PM - 04:20PM | Rm 202, E4 | ZONG, Zhirui | 20 | 0 | 20 | 0 |